
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2022/03/12 11:47:48
// Design Name: 
// Module Name: axi_rmst_bridge
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////

module axi_rmst_bridge #(
                        // Base address of targeted slave
                        parameter  C_M_TARGET_SLAVE_BASE_ADDR    = 32'h800000,
                        // Burst Length. Supports 1, 2, 4, 8, 16, 32, 64, 128, 256 burst lengths
                        parameter integer C_M_AXI_BURST_LEN    = 16,
                        // Width of Address Bus
                        parameter integer C_M_AXI_ADDR_WIDTH    = 32,
                        // Width of Data Bus
                        parameter integer C_M_AXI_DATA_WIDTH    = 64
//                        // Width of User Read Address Bus
//                        parameter integer C_M_AXI_ARUSER_WIDTH    = 1,
//                        // Width of User Read Data Bus
//                        parameter integer C_M_AXI_RUSER_WIDTH    = 1
                        )(
        input   wire    M_AXI_ACLK,
        input   wire    M_AXI_ARESETN,
        output  wire    [C_M_AXI_ADDR_WIDTH-1 : 0] M_AXI_ARADDR,
        output  wire    [7 : 0] M_AXI_ARLEN,
        output  wire    [2 : 0] M_AXI_ARSIZE,
        output  wire    [1 : 0] M_AXI_ARBURST,
        output  wire     M_AXI_ARLOCK,
        output  wire    [3 : 0] M_AXI_ARCACHE,
        output  wire    [2 : 0] M_AXI_ARPROT,
        output  wire    [3 : 0] M_AXI_ARQOS,
        //output  wire    [C_M_AXI_ARUSER_WIDTH-1 : 0] M_AXI_ARUSER,
        output  wire     M_AXI_ARVALID,
        input   wire     M_AXI_ARREADY,
        input   wire     [C_M_AXI_DATA_WIDTH-1 : 0] M_AXI_RDATA,
        input   wire     [1 : 0] M_AXI_RRESP,
        input   wire     M_AXI_RLAST,
        //input   wire     [C_M_AXI_RUSER_WIDTH-1 : 0] M_AXI_RUSER,
        input   wire     M_AXI_RVALID,
        output  wire     M_AXI_RREADY,
        //HY_AXI
        output  wire    HYM_AXI_ACLK,
        output  wire    HYM_AXI_ARESETN,
        input   wire    [C_M_AXI_ADDR_WIDTH-1 : 0]HYM_AXI_ARADDR,
        input   wire    [7 : 0]HYM_AXI_ARLEN,
        input   wire    [2 : 0]HYM_AXI_ARSIZE,
        input   wire    [1 : 0]HYM_AXI_ARBURST,
        input   wire    HYM_AXI_ARLOCK,
        input   wire    [3 : 0]HYM_AXI_ARCACHE,
        input   wire    [2 : 0]HYM_AXI_ARPROT,
        input   wire    [3 : 0]HYM_AXI_ARQOS,
        //input   wire    [C_M_AXI_ARUSER_WIDTH-1 : 0]HYM_AXI_ARUSER,
        input   wire    HYM_AXI_ARVALID,
        output  wire    HYM_AXI_ARREADY,
        output  wire    [C_M_AXI_DATA_WIDTH-1 : 0]HYM_AXI_RDATA,
        output  wire    [1 : 0]HYM_AXI_RRESP,
        output  wire    HYM_AXI_RLAST,
        //output     wire    [C_M_AXI_RUSER_WIDTH-1 : 0]HYM_AXI_RUSER,
        output  wire    HYM_AXI_RVALID,
        input   wire    HYM_AXI_RREADY,
        //
        output  wire    [C_M_AXI_ADDR_WIDTH-1:0]HYM_SLAVE_BASE_ADDR
        
    );
assign HYM_AXI_ACLK = M_AXI_ACLK;
assign HYM_AXI_ARESETN = M_AXI_ARESETN;
assign M_AXI_ARADDR = HYM_AXI_ARADDR;
assign M_AXI_ARLEN = HYM_AXI_ARLEN;
assign M_AXI_ARSIZE = HYM_AXI_ARSIZE;
assign M_AXI_ARBURST = HYM_AXI_ARBURST;
assign M_AXI_ARLOCK = HYM_AXI_ARLOCK;
assign M_AXI_ARCACHE = HYM_AXI_ARCACHE;
assign M_AXI_ARPROT = HYM_AXI_ARPROT;
assign M_AXI_ARQOS = HYM_AXI_ARQOS;
//assign M_AXI_ARUSER = HYM_AXI_ARUSER;
assign M_AXI_ARVALID = HYM_AXI_ARVALID;
assign HYM_AXI_ARREADY = M_AXI_ARREADY;
assign HYM_AXI_RDATA = M_AXI_RDATA;
assign HYM_AXI_RRESP = M_AXI_RRESP;
assign HYM_AXI_RLAST = M_AXI_RLAST;
//assign HYM_AXI_RUSER = M_AXI_RUSER;
assign HYM_AXI_RVALID = M_AXI_RVALID;
assign M_AXI_RREADY = HYM_AXI_RREADY;
//
assign HYM_SLAVE_BASE_ADDR = C_M_TARGET_SLAVE_BASE_ADDR;
endmodule